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document number: mc33689 rev. 7.0, 8/2006 freescale semiconductor technical data freescale semiconductor, inc. reserves the right to change the detai l specifications, as may be required, to permit improvements in the design of its products. ? freescale semiconductor, in c., 2006. all rights reserved. system basis chip with lin transceiver the 33689 is a spi-controlled system basis chip (sbc) that combines many frequently used functions in an mcu-based system plus a local interconnect network (lin) transceiver. applications include power window, mirror, and seat controls. the 33689 has a 5.0 v, 50 ma low dropout regulator with full protection and reporting features. the device provide fu ll spi-readable diagnostics and a selectable timing watchdog for detecting errant operation. the lin transceiver waveshaping circuitry can be disabled for higher data rates. one 50 ma and tw o 150 ma high-side switches with output protection are available to drive inductive or resistive loads. the 150 ma switches can be pulse-width modulated (pwm). two high-voltage inputs are available for contact monitoring or as external wake-up inputs. a current sense operational amplifier is available for load current monitoring. the 33689 has three operational modes: ? normal (all functions available) ? sleep (vdd off, wake-up via lin bus or wake-up inputs) ? stop (vdd on, wake-up via mcu, lin bus, or wake-up inputs) features ? full-duplex spi interface at frequencies up to 4.0 mhz ? lin transceiver capable to 100 kbps with waveshaping capability ? 5.0 v low dropout regulator full fault detection and protection ? one 50 ma and two 150 ma protected high-side switches ? current sense operational amplifier ? the 33689 is compatible with lin 2.0 specification package. ? pb-free packaging designated by suffix code ew figure 1. 33689 simplified application diagram system basis chip with lin 33689d ordering information device temperature range (t a ) package MC33689Ddwb/r2 -40c to 125c 32 soicw mcz33689dew/r2 dwb suffix ew suffix (pb-free) 98arh99137a 32-pin soicw v pwr spi mosi sck miso 5.0 v mcu 33689 bus vs1 vs2 vdd hs3 l1 l2 hs1 hs2 e+ lin int rst mosi sclk miso txd rxd out gnd in cs cs wdc e- tgnd agnd v dd vcc
analog integrated circuit device data 2 freescale semiconductor 33689 internal block diagram internal block diagram figure 2. 33689 simplifi ed internal block diagram lin l1 l2 vdd hs2 hs3 e+ e- rxd txd out mosi miso sclk spi and mode control vcc 5.0 v/50 ma in voltage regulator lin physical interface window watchdog reset control pre-driver gnd agnd tgnd vs1 current sense op amp cs int wdc rst vs1 hs1 vs2
analog integrated circuit device data freescale semiconductor 3 33689 pin connections pin connections figure 3. 33689 32-soicw pin connections table 1. 33689 32-soicw pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 19 . pin pin name formal name pin function definition 1, 3, 14 nc no connect n/a no internal connection to these pins. 2, 4 l1, l2 level inputs 1 and 2 input inputs from external switches or from logic circuitry. 5 ? 7 hs3 ? hs1 high-side driver outputs 3 through 1 output high-side (hs) drive power outputs. spi-controlled for driving system loads. 8, 9, 24, 25 tgnd thermal ground n/a thermal ground pins for the device. 10 vs2 voltage supply 2 input supply pin for the high-side sw itches hs1, hs2, and hs3. 11 lin lin bus input / output bidirectional pin that represents the single-wire bus transmitter and receiver. 12 gnd ground n/a electrical ground pin for the device. 13 vs1 voltage supply 1 input supply pin for the 5.0 v regulator, the lin physical interface, and the internal logic. 15 vdd 5.0 v regulator output output output of the 5.0 v regulator. 16 agnd analog ground n/a analog ground pin for voltage regulator and current sense operational amplifier. 17 vcc power supply in input 5.0 v supply for the internal current sense operational amplifier. 18 out amplifier output output output of the internal current sense operational amplifier. 19 e - amplifier inverted input input inverted input of the internal current sense operational amplifier. 20 e+ amplifier non-inverted input input non-inverted input of the internal current sense operational amplifier. 21 wdc watchdog configuration (active low) reference configuration pin for the watchdog timer. txd 1 miso mosi sclk tgnd tgnd in rst wdc e+ out vcc e - cs rxd int nc hs3 hs2 hs1 tgnd tgnd vs2 lin gnd vs1 vdd agnd nc l2 l1 nc 8 9 10 11 12 13 14 15 16 3 4 5 6 7 2 32 25 24 23 22 21 20 19 18 17 30 29 28 27 26 31
analog integrated circuit device data 4 freescale semiconductor 33689 pin connections 22 rst reset output (active low) output 5.0 v regulator and watchdog reset output pin. 23 in pwm input control input external input pwm control pin fo r high-side switches hs1 and hs2. 26 sclk serial data clock input clock input for the spi of the 33689. 27 mosi master out slave in input spi data received by the 33689. 28 miso master in slave out output spi data sent to the mcu by the 33689. when cs is high, pin is in the high-impedance state. 29 cs chip select (active low) input spi control chip select input pin. 30 int interrupt output (active low) output this output pin reports faults to the mcu when an enabled interrupt condition occurs. 31 rxd receiver output output receiver output of the lin interface and reports the state of the bus voltage. 32 txd transmitter input input transmitter input of the lin interface and controls the state of the bus output. table 1. 33689 32-soicw pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 19 . pin pin name formal name pin function definition
analog integrated circuit device data freescale semiconductor 5 33689 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings v pwr supply voltage at vs1 and vs2 continuous transient (load dump) v supdc v suptr - 0.3 to 27 40 v supply voltage at vdd and vcc v dd - 0.3 to 5.5 v output current at vdd i dd internally limited a logic input voltage at mosi, sclk, cs , in, and txd v inlog - 0.3 to v dd + 0.3 v logic output voltage at miso, int , rst , and rxd v outlog - 0.3 to v dd + 0.3 v input voltage at e+ and e - v e+ / v e - - 0.3 to 7.0 v input current at e+ and e - i e+ / i e - 20 ma output voltage at out v out - 0.3 to v cc + 0.33 v output current at out i out 20 ma input voltage at l1 and l2 dc input with a 33 k ? resistor transient input with external compon ent (per iso7637 specification) (see figure 4 , page 6 ) v lxdc v lxtr -18 to 40 100 v input / output voltage at lin dc voltage transient input voltage with specified external component (per iso7637 specification) (see figure 4 , page 6 ) v busdc v bustr -18 to 40 -150 to 100 v dc output voltage at hs1 and hs2 positive negative v hs+ v hs - v vs2 + 0.3 internally clamped v dc output voltage at hs3 v hs3 - 0.3 to v vs2 + 0.3 v esd voltage, human body model (1) gnd configured as ground. tgnd and agnd configured as i/o pins lin, l1, and l2 all other pins v esd1 4000 2000 v esd voltage, charge device model (1) corner pins (pins 1, 16, 17, and 32) all other pins (pins 2 ? 15 and 18 ? 31) v esd2 750 500 v notes 1. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the charge device model, robotic (c zap = 4.0 pf).
analog integrated circuit device data 6 freescale semiconductor 33689 electrical characteristics maximum ratings thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 165 c thermal resistance, junction-to-ambient r ja 80 c/ w peak package reflow temperature during solder mounting (2) t solder 240 c notes 2. pin soldering temperature is for 10 seconds maximum duration. not designed for immers ion soldering. exceeding these limits may cause permanent damage to the device. figure 4. iso 7637 test setup for lin, l1, and l2 pins table 2. maximum ratings(continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit lin, l1, l2 transient pulse gnd generator 1.0 nf (note) 10 k ? note waveform per iso 7637-1. test pulses 1, 2, 3a, and 3b. gnd 33689d tgnd agnd
analog integrated circuit device data freescale semiconductor 7 33689 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit vs1 and vs2 input pins (device power supply) supply input voltage nominal dc load dump jump start (3) v sup v supld v supjs 5.5 ? ? ? ? ? 18 40 27 v supply input current (4) normal mode, i out at vdd = 10 ma, lin recessive state sleep mode, vdd off, v sup 13.5 v stop mode, vdd on with i out < 100 a, v sup 13.5 v i sup(norm) i sleep i stop ? ? ? 5.0 35 60 8.0 45 75 ma a a input threshold voltage (normal mode, interrupt generated) fall early warning, bit vsuv set overvoltage warning, bit vsov set v suvew v sovw 5.7 18 6.1 19.75 6.6 20.5 v hysteresis (5) vsuv flag vsov flag v hys ? ? 1.0 220 ? ? v mv vdd output pin (external 5.0 v output for mcu use) (6) output voltage i dd from 2.0 ma to 50 ma, 5.5 v < v sup < 27 v v ddout 4.75 5.0 5.25 v dropout voltage (7) i dd = 50 ma v dddrop ? 0.1 0.2 v output current limitation (8) i dd 50 120 200 ma overtemperature pre-warning (junction) normal mode, interrupt generated, bit vddt set t pre 120 135 160 c thermal shutdown (junction) normal mode t sd 165 170 ? c notes 3. device is fully functional. all features are operating. an overtemperature fault may occur. 4. total current (i vs1 + i vs2 ) at vs1 and vs2 pins is measured at the ground pins. 5. parameter guaranteed by design; however, it is not production tested. 6. specification with external capacitor 2.0 f < c < 10 f and 200 m ? esr 10 ? . normal mode. low esr elec trolytic capacitor values up to 47 f can be used. 7. measured when the voltage has dropped 100 mv below its nominal value. 8. internally limited. total 5.0 v regulator current. a 5.0 ma current for the current sense oper ational amplifier operation is included. digital outputs are supplied from vdd.
analog integrated circuit device data 8 freescale semiconductor 33689 electrical characteristics static electrical characteristics vdd output pin (5.0 v output for mcu use) (continued) (9) temperature threshold difference normal mode (t sd - t pre ) t diff 20 30 40 c v sup range for reset active 0.5 v < v dd < v dd (v rst th ) v supr 4.0 ? ? v line regulation 5.5 v < v sup < 27 v, i dd = 10 ma v lr1 ? 20 150 mv load regulation 1.0 ma < i dd < 50 ma v ld1 ? 10 150 mv vdd output pin in stop mode output voltage (10) i dd 2.0 ma v dds 4.75 5.0 5.25 v output current capability (11) i dds 4.0 8.0 14 ma line regulation 5.5 v < v sup < 27 v, i dd = 2.0 ma v lr s ? 10 100 mv load regulation 1.0 ma < i dd < 5.0 ma v lds ? 40 150 mv rst output pin in normal and stop modes reset threshold voltage v rst th 4.5 4.7 v dd - 0.2 v low-level output voltage i o = 1.5 ma, 4.5 v < v sup < 27 v v ol 0.0 ? 0.9 v high-level output current 0.0 v < v out < 0.7 v dd i oh ? - 275 ? a reset pulldown current internally limited, v dd < 4.0 v, v rst = 4.6 v i pd rst 1.5 ? 8.0 ma in input pin low-level input voltage v il - 0.3 ? 0.3 v dd v high-level input voltage v ih 0.7 v dd ? v dd + 0.3 v input current 0.0 v < v in < v dd i in -10 ? 10 a notes 9. specification with external capacitor 2.0 f < c < 10 f and 200 m ? esr 10 ? . normal mode. low esr elec trolytic capacitor values up to 47 f can be used. 10. when switching from normal mode to stop mode or from stop mode to normal mode, the voltage can vary within the output voltage specification. 11. when i dd is above i dds , the 33689 enters the reset mode. table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33689 electrical characteristics static electrical characteristics miso spi output pin low-level output voltage i out = 1.5 ma v ol 0.0 ? 1.0 v high-level output voltage i out = 250 a v oh v dd - 0.9 ? v dd v tri-stated miso output leakage current 0.0 v < v miso < v dd i hz - 2.0 ? 2.0 a mosi, sclk, cs spi input pins low-level input voltage v il - 0.3 ? 0.3 v dd v high-level input voltage v ih 0.7 v dd ? v dd + 0.3 v pullup input current on cs v cs = 4.0 v i pu cs -100 ? - 20 a mosi, sclk input current 0.0 v < v in < v dd i in -10 ? 10 a int output pin low-level output voltage i o = 1.5 ma v ol 0.0 ? 0.9 v high-level output voltage i o = - 250 a v oh v dd - 0.9 ? v dd v wdc pin external resistor range r ext 10 ? 100 k ? hs1 and hs2 high-side output pins output clamp voltage i out = -100 ma v cl - 6.0 ? ? v output drain-to-source on resistance t a = 25c, i out -150 ma t a = 125c, i out -150 ma t a = 125c, i out -120 ma r ds(on) ? ? ? 2.0 ? 3.0 2.5 4.5 4.0 ? output current limitation i lim 300 430 600 ma overtemperature shutdown (12) t otsd 155 ? 190 c output leakage current i leak ? ? 10 a notes 12. when overtemperature occurs, switch is turned off and latc hed off. flag is set in spi register. refer to description on page 26 . table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33689 electrical characteristics static electrical characteristics hs3 high-side output pin output drain-to-source on resistance t a = 25c, i out - 50 ma t a = 125c, i out - 50 ma t a = 125c, i out - 30 ma r ds(on) ? ? ? 5.5 ? 10 7.0 10 14 ? output current limitation i lim 60 100 200 ma overtemperature shutdown (13) t otsd 155 ? 190 c output leakage current i leak ? ? 10 a out, e+, and e- pins at current sense operational amplifier input voltage ? rail-to-rail at e+ and e- v imc - 0.1 ? v cc + 0.1 v output voltage range at out with 1.0 ma output load current with 5.0 ma output load current v out 0.1 0.3 ? ? v cc - 0.1 v cc - 0.3 v input bias current i b ? ? 250 na input offset voltage v io -15 ? 15 mv input offset current i o -100 ? 100 na l1 and l2 input pins low-voltage detection input threshold voltage 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v thl 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.5 3.7 v high-voltage detection input threshold voltage 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v thh 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.5 4.7 v input hysteresis 5.5 v < v sup < 27 v v hys 0.5 ? 1.3 v input current - 0.2 v < v in < 40 v i in -10 ? 10 a notes 13. when overtemperature occurs, switch is turned off and latc hed off. flag is set in spi register. refer to description on page 26 . table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33689 electrical characteristics static electrical characteristics rxd output pin (lin physical layer) low-level output voltage i out 1.5 ma v ol 0.0 ? 0.9 v high-level output voltage i out 250 a v oh 3.75 ? 5.25 v txd input pin (lin physical layer) low-level input voltage v il ? ? 1.5 v high-level input voltage v ih 3.5 ? ? v input hysteresis v inhys 50 145 300 mv pullup current source 1.0 v < v txd < 3.5 v i putxd -100 ? - 20 a lin physical layer, transceiver transceiver output voltage dominant state, txd low, external bus pullup 500 ? recessive state, txd high, i out = 1.0 a v lindom v linrec ? v sup -1.0 ? ? 1.4 ? v pullup resistor to vsup in normal mode and in sleep and stop modes when not disabled by spi r pu 20 30 47 k ? pullup current source in sleep and stop modes when pullup disabled by spi i pulin ? 1.3 ? a output current shutdown threshold i outsd 50 75 150 ma leakage output current to gnd vs1 and vs2 disconnected, v lin = 18 v recessive state, 8.0 v < v sup < 18 v, 8.0 v < v lin < 18 v gnd disconnected, v gnd = v sup , v lin = -18 v i busleak ? 0.0 -1.0 1.0 3.0 ? 10 20 1.0 a a ma lin physical layer, receiver receiver input threshold voltage dominant state, txd high, rxd low recessive state, txd high, rxd high center (v busdom - v busrec ) / 2 hysteresis (v busdom - v busrec ) v busdom v busrec v buscnt v bushys 0.0 0.6 0.475 ? ? ? 0.5 ? 0.4 1.0 0.525 0.175 v sup bus wake-up threshold v buswu ? 0.5 ? v sup table 3. static electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33689 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unles s otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit spi interface characteristics spi operation frequency f spi 0.25 ? 4.0 mhz sclk clock period t pscl k 250 ? n/a ns sclk clock high time t wsclkh 125 ? n/a ns sclk clock low time t wsclkl 125 ? n/a ns falling edge of cs to rising edge of sclk t lead 100 ? n/a ns falling edge of sclk to cs rising edge t lag 100 ? n/a ns mosi to falling edge of sclk (data setup time) t si (su) 40 ? n/a ns falling edge of sclk to mosi (data hold time) t si (hold) 40 ? n/a ns miso rise time (14) c l = 220 pf t rso ? 25 50 ns miso fall time (14) c l = 220 pf t fso ? 25 50 ns time from falling or rising edge of cs to: (14) miso low impedance (enable) miso high impedance (disable) t so (en) t so (dis) 0.0 0.0 ? ? 50 50 ns time from rising edge of sclk to miso data valid (14) 0.2 v dd miso 0.8 v dd , c l = 100 pf t valid 0.0 ? 50 ns rst output pin in normal and stop modes reset duration after vdd high t dur rst 0.65 1.0 1.35 ms wdc pin watchdog period accuracy using an extern al resistor (excluding resistor tolerances) (15) acc wdc -15 ? 15 % watchdog time period (15) 10 k ? external resistor 100 k ? external resistor no external resistor, wdc open, normal mode t wdc ? ? 107 10.558 99.748 160 ? ? 215 ms notes 14. parameter guaranteed by design; however, it is not production tested. 15. watchdog time period calculation formula: t wdc = 0.991 * r + 0.648 (r in k ? and t wdc in ms).
analog integrated circuit device data freescale semiconductor 13 33689 electrical characteristics dynamic electrical characteristics current sense operational amplifier supply voltage rejection ratio (16) svr 60 ? ? db common mode rejection ratio (16) cmr 70 ? ? db gain bandwidth (16) gbp 1.0 ? ? mhz output slew rate sr 0.5 ? ? v/ s phase margin phmo 40 ? ? deg. open loop gain (16) olg ? 85 ? db l1 and l2 input pins wake-up filter time (16) t wuf 8.0 20 38 s state machine timing delay between cs low-to-high transition (at end of spi stop command) and stop mode activation (16) minimum watchdog period no watchdog selected maximum watchdog period t stop 1.4 6.0 12 ? ? ? 5.0 30 50 s interrupt low-level duration t int 7.0 10 13 s internal oscillator frequency accuracy (all modes, for information only) f osc - 35 ? 35 % normal request mode time-out (normal request mode) t nrtout 97 150 205 ms delay between spi command and hs1 or hs2 turn on (17) , (18) normal mode, v sup > 9.0 v, v hs 0.2 v vs2 t shson ? ? 20 s delay between spi command and hs1 or hs2 turn off (17) , (18) normal mode, v sup > 9.0 v, v hs 0.8 v vs2 t shsoff ? ? 20 s delay between spi command and hs3 turn on (17) , (19) normal mode, v sup > 9.0 v, v hs 0.2 v vs2 t shson ? ? 20 s delay between spi command and hs3 turn off (17) , (19) normal mode, v sup > 9.0 v, v hs 0.8 v vs2 t shsoff ? ? 20 s delay between normal request and normal mode after a watchdog trigger command (normal request mode) (16) t snr2n 7.0 15 30 s delay between cs wake-up ( cs low to high) in stop mode and: normal request mode, vdd on and rst high first accepted spi command t wu cs t wuspi 15 90 40 ? 80 n/a s delay between interrupt pulse in stop mode after wake-up and first accepted spi command t s1stspi 30 ? n/a s minimum time between rising and falling edge on the cs t 2 cs 15 ? ? s notes 16. parameter guaranteed by design; however, it is not production tested. 17. when in input is set to high, delay starts at falling edge of clock cycle #8 of the spi command and start of device activati on/deactivation. 30 ma load on high-side switches. excluding rise or fall time due to external load. 18. when in is used to control the high-side switc hes, delays are measured between in and hs1 or hs2 on / off. 30 ma load on high-side switches, excluding rise or fa ll time due to external load. 19. delay between turn on or turn off command and hs on or hs off, excluding rise or fa ll time due to external load. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unles s otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 33689 electrical characteristics dynamic electrical characteristics lin physical layer: bus driver timing characteristics for normal slew rate (20) propagation delay txd to lin (21) dominant state minimum threshold (50% txd to 58.1% v sup ) dominant state maximum threshold (50% txd to 28.4% v sup ) recessive state minimum threshold (50% txd to 42.2% v sup ) recessive state maximum threshold (50% txd to 74.4% v sup ) t dommin t dommax t recmin t recmax ? ? ? ? ? ? ? ? 50 50 50 50 s propagation delay symmetry t dommin - t recmax t dommax - t recmin dt1s dt2s -10.44 ? ? ? ? 11 s lin physical layer: bus driver timing characteristics for slow slew rate (20) propagation delay txd to lin (22) dominant state minimum threshold (50% txd to 61.6% v sup ) dominant state maximum threshold (50% txd to 25.1% v sup ) recessive state minimum threshold (50% txd to 38.9% v sup ) recessive state maximum threshold (50% txd to 77.8% v sup ) t dommin t dommax t recmin t recmax ? ? ? ? ? ? ? ? 100 100 100 100 s propagation delay symmetry t dommin - t recmax t dommax - t recmin dt1s dt2s - 22 ? ? ? ? 23 s lin physical layer: bus dr iver fast slew rate lin high slew rate (programming mode) dv/dt fast ? 13 ? v/ s lin physical layer, transceiver output current shutdown delay (23) t outdly ? 10 ? s notes 20. 7.0 v < v sup < 18 v, bus load c0 and r0 1.0 nf/1.0 k ? , 6.8 nf / 660 ? , 10 nf / 500 ? . 50% of txd signal to li n signal threshold. see figure 5 , page 16 . 21. see figure 7 , page 17 . 22. see figure 8 , page 17 . 23. parameter guaranteed by design; however, it is not production tested. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unles s otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33689 electrical characteristics dynamic electrical characteristics lin physical layer: receiver characteristics and wake-up timings propagation delay lin to rxd (24) dominant state (lin low to rxd low) recessive state (lin high to rxd high) symmetry ( t rdom - t rrec ) t rdom t rrec t rsym ? ? - 2.0 3.0 3.0 ? 6.0 6.0 2.0 s bus wake-up deglitcher (sleep and stop modes) (25) t propwl 30 70 90 s bus wake-up event reported from sleep mode (26) from stop mode (27) t wu t wu ? ? 30 20 ? ? s notes 24. measured between lin signal threshold v inl or v inh and 50% of rxd signal. 25. see figures 9 and 10 , page 18 . 26. t wu is typically 2 internal cloc k cycles after a lin rising edge is detected. in sleep mode, the measurement is done without a cap acitor connected to the regulator. the delay is measured between the v sup /2 rising edge of the lin bus and when v dd reaches 3.0 v. the v dd rise time is strongly dependent upon the decoupling capacitor at v dd pin. see figure 9 , page 18 . 27. t wu is typically 2 internal clock cycles after a lin rising edge is detected. in stop mode, the delay is measured between the v sup /2 rising edge of the lin bus and the falling edge of the int pin. see figure 10 , page 18 . table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 5.5 v v sup 18 v, - 40 c t a 125 c, gnd = 0.0 v unles s otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33689 electrical characteristics timing diagrams timing diagrams figure 5. test circui t for timing measurements figure 6. spi timing characteristics txd rxd 33689 vs1/vs2 lin v pwr r0 c0 r0/c0 combinations: 1.0 k ? /1.0 nf 660 ? /6.8 nf 500 ? /10 nf gnd tgnd agnd di 0 do 0 undefined don?t care di 7 don?t care t lead t si(hold) t si(su) t lag t psclk t wsclkh t wsclkl t valid do 7 t so(dis) cs sclk mosi miso t so(en) note incoming data at mosi pin is sampled by the 33689 at sclk falling edge. outgoing data at miso is set by the 33689 at sclk rising edge (after t valid delay time).
analog integrated circuit device data freescale semiconductor 17 33689 electrical characteristics timing diagrams figure 7. timing ch aracteristics for normal lin output slew rate figure 8. timing characteristi cs for slow lin output slew rate txd rxd lin v linrec t dommin recessive state t rdom t rrec t dommax t recmax t recmin 40% v sup 60% v sup 58.1% v sup 28.4% v sup 74.4% v sup 42.2% v sup dominant state txd rxd v linrec t dommin recessive state t rdom t dommax t recmax t recmin 40% v sup 60% v sup 61.6% v sup 25.1% v sup 77.8% v sup 38.9% v sup t rrec dominant state lin
analog integrated circuit device data 18 freescale semiconductor 33689 electrical characteristics timing diagrams figure 9. lin bus wake-up behavior, sleep mode figure 10. lin bus wake-up behavior, stop mode vdd lin v linrec dominant level recessive state 0.4 v sup t propwl t wu int lin v linrec dominant state recessive state 0.4 v sup t propwl t wu
analog integrated circuit device data freescale semiconductor 19 33689 functional description introduction functional description introduction a system basis chip (sbc) is a monolithic ic combining many functions found in st andard microcontroller-based systems; e.g., power management, communication interface, system protection, and diagnostics. the 33689 is a spi-controlled sbc combining many functions with a lin transceiver for slave node applications. the 33689 has a 5.0 v, 50 ma regulator with undervoltage reset, output current limiting, overtemperature pre-warning, and thermal shutdown. an externally selectable timing window watchdog is also included. the lin transceiver has waveshaping that can be disabled when high data rates are warranted. a single 50 ma and two 150 ma fully protected high-s ide switches with output clamping are available for switching inductive or resistive loads. the 150 ma switches are pwm capable. two high-voltage inputs can be used to monitor switches or provide external wake-up. an internal current sense operational amplifier is available for load current monitoring. functional pin description level 1 and level 2 input pins (l1 and l2) these pins are used to sense external switches and to wake up the 33689 from sleep or stop mode. during normal mode, the state of these pins can be read through the spi register. (refer to the section entitled spi interface and register description on page 24 for information on the spi register.) high-side driver output pins 1 and 2 (hs1 and hs2) these two high-side switches are able to drive loads such as relays or lamps. they are protected against overcurrent and overtemperature and include internal clamp circuitry for inductive load protection. switch control is done through selecting the correct bit in the spi register. hs1 and hs2 can be pwm-ed if required through the in input pin. the internal circuitry that drives both high-side switches is an and function between the spi bit hs1 (or hs2) and the in input pin. if no pwm control is required, the in pin must be connected to the vdd pin. high-side driver output pin 3 (hs3) this high-side switch can be used to drive small lamps, hall sensors, or switch pull up resistors. control is done through the spi register only. no direct pwm control is possible on this pin. this high-side switch features current limit to protect it against overcurrent and short circuit conditions. it is also protected against overtemperature. voltage supply pins 1 and 2 (vs1 and vs2) the 33689 is supplied from a battery line or other supply source through the vs1 and vs2 pins. an external diode is required to protect against negative transients and reverse battery. the 33689 can operat e from 4.5 v and under the jump start condition at 27 v dc. device functionality is guaranteed down to 4.5 v at vs1 and vs2 pins. these pins sustain standard automotive voltage conditions such as load dump at 40 v. lin bus pin (lin) the lin pin represents the single-wire bus transmitter and receiver. it is suited for autom otive bus systems and is based on the lin bus specification. voltage source pin (vdd) the vdd pin is the 5.0 v supply pin for the mcu and the current sense operational amplifier. current sense operational amplifier pins (e+, e - , vcc, and out) these are the pins of the single-supply current sense operational amplifier. ? the e+ and the e- input pins are the non-inverting and inverting inputs of the current sense operational amplifier, respectively. ? the out pin is the output pin of the current sense operational amplifier. ? the vcc pin is the + 5.0 v single-supply connection for the current sense operational amplifier. the current sense operational amplifier is enabled in normal mode only. watchdog configuration pin ( wdc ) the wdc pin is the configuration pin for the internal watchdog. a resistor is connected to this pin. the resistor value defines the watchdog period. if the pin is left open, the watchdog period is fixed to its default value (150 ms typical). if no watchdog function is required, the wdc pin must be connected to gnd.
analog integrated circuit device data 20 freescale semiconductor 33689 functional description functional pin description reset output pin ( rst ) the rst pin is the 5.0 v regulator and watchdog reset output pin. pwm input control pin (in) the in pin is the external pwm control pin for the hs1 and hs2 high-side switches. serial data clock pin (sclk) the sclk pin is the spi clock input pin. miso data changes on the negative transi tion of the sclk. mosi is sampled on the positive edge of the sclk. master out slave in pin (mosi) the mosi pin receives spi dat a from the mcu. this data input is sampled on the positive edge of sclk. master in slave out pin (miso) the miso pin sends data to an spi-enabled mcu. data on this output pin changes on the negative edge of the sclk. when cs is high, this pin enters the high-impedance state. chip select pin ( cs ) the cs pin is the chip select input pin for spi use. when this signal is high, spi signals are ignored. asserting this pin low starts an spi transaction. the transaction is completed when this signal returns high. interrupt output pin ( int ) the int pin is used to report 33689 faults to the mcu. interrupt pulses are generated for: ? voltage regulator temperature pre-warning ? hs1, hs2, or hs3 thermal shutdown ? vs1 or vs2 overvoltage (20 v typical) ? vs1 or vs2 undervoltage (6.0 v typical) if an interrupt is generated, then when the next spi read operation is performed bit d7 in the spi register will be set to logic [1] and bits d6 : d0 will report the interrupt source. in cases of wake-up from the stop mode, int is set low in order to signal to the mcu that a wake-up event from the l1, l2, or lin bus pin has occurred. receiver output pin (rxd) the rxd pin is the receiver ou tput of the lin interface and reports the state of the bus voltage (rxd low when lin bus is dominant, rxd high when lin bus is recessive). transmitter input pin (txd) the txd pin is the transmitter input of the lin interface and controls the state of the bus output (dominant when txd is low, recessive when txd is high). ground pins (gnd, tgnd, and agnd) the 33689 has three different types of ground pins. ? the gnd pin is the electrical ground pin for the device. ? the agnd is the analog ground pin for the voltage regulator and current sense operational amplifier. ? the four tgnd pins are the thermal ground pins for the device. important the gnd, the agnd, and the four tgnd pins must be connected together to a ground external to the 33689.
analog integrated circuit device data freescale semiconductor 21 33689 functional description functional internal block description functional internal block description window watchdog the window watchdog can be configured using an external resistor at wdc pin. the watchdog is cleared through mode1 and mode2 bit in the spi register (refer to table 2 , page 24 ; also refer to the section entitled functional pin description on page 19 . a watchdog clear is only allowed in the open window (see figure 1 ). if the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the rst pin and reset the whole device. note the watchdog clear in normal request mode (150 ms) (first watchdog clear) has no window. figure 1. window watchdog operation window watchdog configuration if the wdc pin is left open, the default watchdog period is selected (typ. 150 ms). if no watchdog function is required, the wdc pin must be connected to gnd. the watchdog timer?s period is calculated using the following formula: t wdc = 0.991 * r +0.648 (with r in k ? and t wdc in ms). vdd voltage regulator the 33689 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the mcu. the on-chip regulator co nsist of two elements, the main voltage regulator and the low-voltage reset circuit. the vdd regulator accepts an unregulated input supply and provides a regulated v dd supply to all digital sections of the device. the output of the regulator is also connected to the vdd pin to provide the 5.0 v to the microcontroller. current limit (overcurrent) protection the voltage regulator has current limit to protect the device against overcurrent and short circuit conditions. overtemperature protection the voltage regulator also features overtemperature protection that has an overte mperature warning (interrupt - vddt) and an overtemperature shutdown. stop mode during stop mode, the stop mode regulator supplies a regulated output voltage. th e stop mode regulator has a limited output current capability. sleep mode in sleep mode, the voltage regulator external vdd is turned off. vdd voltage regulator temperature prewarning vdd voltage regulator temper ature prewarning (vddt) is generated if the voltage regulato r temperature is above the t pre threshold. it will set the vddt bit in the spi register and an interrupt will be initiated. the vddt bit remains set as long as the error condition is present. during sleep and stop modes the vdd voltage regulator temperature prewarning circuitry is disabled. high-side switch thermal shutdown the high-side switch thermal shutdown hsst is generated if one of the high-si de switches hs1 : hs3 is above the hsst threshold. it will shutdown all high-side switches and set the hsst flag in the spi register, and an interrupt will be initiated. the hsst bit remains set as long as the error condition is present. during sleep and stop modes the high- side switch the rmal shutdown circuitry is disabled. window closed. window open t wdc * 50% t wdc * 50% watchdog period for watchdog clear no watchdog clear allowed t wdc
analog integrated circuit device data 22 freescale semiconductor 33689 functional description functional device operation functional device operation operational modes as described below and depicted in figure 1 below and table 1 on page 23 , the 33689 has three operational modes: normal, sleep, and stop. oper ational modes are controlled by mode1 and mode2 bits in the spi register (refer to logic commands and registers on page 24 ). in additional, there are two transitional modes: reset and normal request. reset mode at power up, the 33689 switches automatically to reset mode for 1 ms if v dd goes high. if v dd stays low, after 150 ms the 33689 goes in sleep mode. normal request mode before entering in normal request mode, the 33689 stays for 1 ms in reset mode. in this mode, the lin bus can transmit and receive information. figure 1. 33689 modes state diagram power reset stop normal sleep vdd high & reset counter (1.0 ms) expired & watchdog selected 33689 power-up vdd low or (normal request timeout occurs [150 ms] & watchdog selected) wake-up & watch- dog selected stop command sleep command wake-up vdd low watchdog trigger vdd high & reset counter (1.0 ms) expired & watchdog not selected vdd low or (watchdog fail & watchdog selected) legend watchdog selected: external resistor between wdc pin and gnd or wdc pin open. watchdog not selected: wdc pin connected to gnd. watchdog fail: watchdog trigger occurs in closed window or no spi watchdog trigger command. stop command: spi stop command. sleep command: spi sleep request followed by spi sleep command. wake-up: l1 or l2 state change or lin bus wake-up or cs rising edge. vdd low (150 ms) expired & vsuv bit = logic [0] wake-up & watchdog not selected down normal request
analog integrated circuit device data freescale semiconductor 23 33689 functional description functional device operation normal mode in normal mode, the 33689 has slew rate and timing compatible with the lin protocol specification. the lin bus can transmit and receive information. the v dd regulator is on and the watchdog function can be enabled. sleep and stop mode to safely enter sleep or stop modes and to ensure that these modes are not inadvert ently entered due to noise issues during spi transmissi on, a dedicated sequence must be sent twice: data with the bi ts controlling the lin bus and the device mode. entering sleep mode first and second spi commands ( with bit d6 = 1, d7 = 1, d5 = 0 or 1, d1 = 0, and d0 = 0) 11x00000 must be sent. entering stop mode first and second spi commands ( with bit d6 = 1, d7 = 1, d5 = 0 or 1, d1 = 0, and d0 = 1) 11x00001 must be sent. sleep or stop modes are entered after the second spi command. register bit d5 must be set accordingly. table 1. operational modes and associated functions device mode vdd voltage regulator wake-up capabilities rst output watchdog function hs1, hs2, hs3 lin interface operational amplifier reset vdd: on n/a low for 1.0 ms typical, then high (if vdd above threshold) disabled off recessive only not active normal request vdd: on n/a high. active low if vdd undervoltage occurs and if normal request timeout (if watchdog enabled) 150 ms timeout if watchdog enabled on or off transmit and receive not active normal vdd: on n/a high. active low if vdd undervoltage occurs or if watchdog fail (if watchdog enabled) window watchdog if enabled on or off transmit and receive active stop vdd: on (limited current capability) lin and state change on l1:l2 inputs normally high. active low if vdd undervoltage occurs disabled off recessive state with wake capability not active sleep vdd: off (set to 5.0 v after wake-up to enter normal request) lin and state change on l1:l2 inputs low. go to high after wake-up and vdd within specification disabled off recessive state with wake capability not active
analog integrated circuit device data 24 freescale semiconductor 33689 functional description functional device operation logic commands and registers spi interface and register description as shown in figure 2 , the spi is an 8-bit spi. all data is sent as bytes. the msb, d7, is sent first. the minimum time between two rising edges on the cs pin is 15 s. during an spi data communication, the state of miso reports the state of the 33689 at time of a cs high-to-low transition. the status flags are latched at a cs high-to-low transition. figure 2. data format description the following tables describe the spi register bits, showing reset values and reset conditions. spi register: write control bits linsl2 and linsl1 ? lin baud rate and low-power mode pre-selection bits these bits select the lin slew rate and requested low- power mode in accordance with table 3 . reset clears the linsl2 : 1 bits. mosi miso bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 d0 d1 d2 d3 d4 d5 d6 d7 table 2. spi re gister overview read / write information msb bits lsb d7 d6 d5 d4 d3 d2 d1 d0 write linsl2 linsl1 lin-pu hs3 hs2 hs1 mode2 mode1 read intsrc (1) linwu or linfail vsov vsuv or batfail (2) vddt hsst l2 l1 write reset value 000 0 00?? write reset condition por, reset por, reset por por, reset por, reset por, reset ?? notes 1. d7 signals interrupt source. after interrupt occurs, if d7 is a logic [1] d6 : d0 indicate the interrupt source. if d7 is a l ogic [0] no interrupt has occurred and d6 : d0 report real-time status. 2. the first spi read after a 33689 reset returns the batfail status flag bit d4. table 3. lin slew rate control and device low power mode pre-selection bits (d7 and d6) linsl2 linsl1 description 0 0 lin slew rate normal (baud rate up to 20 kbps) 0 1 lin slew rate slow (baud rate up to 10 kbps) 1 0 lin slew rate fast (for program download, baud rate up to 100 kbps) 1 1 low power mode (sleep or stop mode) request, no change in lin slew rate
analog integrated circuit device data freescale semiconductor 25 33689 functional description functional device operation lin-pu ? lin pullup enable bit this bit controls the lin pullup resistor during sleep and stop modes in accordance with table 4 . reset clears the lin-pu bit. hs3: hs1 ? high-side h3 : hs1 enable bits these bits enable the hs3 : hs1 bits in accordance with table 5 . reset clears the hsx bit. note if no pwm on hs1 and hs2 is required, the in pin must be connected to the vdd pin. mode2 and mode1 ? mode section bits the mode2 and mode1 bits control the 33689 operating modes in accordance with table 6 . to safely enter sleep or stop mode and to ensure that these modes are not affected by noise issue during spi transmission, the sleep / stop commands require two spi transmissions. sleep mode sequence the sleep command, as shown in table 7 , must be sent twice. stop mode sequence the stop command, as shown in table 8 , must be sent twice. table 4. lin pullup termination control bit (d5) lin-pu description 0 30 k ? pullup connected in sleep and stop mode 1 30 k ? pullup disconnected in sleep and stop mode table 5. high-side switches control bits (d4, d3, and d2) hs3 description hs2 description hs1 description 0 hs3 off 0 hs2 off 0 hs1 off 1 hs3 on 1 hs2 on (if in = 1) 1 hs1 on (if in = 1) table 6. mode control bits (d1 and d0) mode2 mode1 description 0 0 sleep mode (3) 0 1 stop mode 1 0 normal mode + watchdog clear (4) 1 1 normal mode notes 3. special spi command and sequence is implemented in order to avoid going into sleep or stop mode with a single 8-bit spi command. refer to tables 7 and 8 . 4. when a logic [0] is written to mode1 bit while mode2 bit is written as a logic [1]. after the spi command is completed, mode1 bit is set to logic [1] and the 33689 stays in normal mode. in order to set the 33689 in sleep mode, both mode1 and mode2 bits must be written in the same 8-bit spi command. the watchdog clear on normal request mode (150 ms) has no window. table 7. sleep command bits linsl2 linsl1 lin-pu hs3 hs2 hs1 mode2 mode1 11x0000 0 x = don?t care. table 8. stop command bits linsl2 linsl1 lin-pu hs 3hs2hs1mode2mode1 11x000 0 1 x = don?t care.
analog integrated circuit device data 26 freescale semiconductor 33689 functional description functional device operation spi register: read control bits intscr ? register content flags or interrupt source the intscr bit, as shown in table 9 , indicates if the register contents reflect the fl ags or an interrupt / wake-up source. linwu / linfail ? lin bus status flag bit this bit indicates a lin wake-up condition or a lin overcurrent/overtemperature in accordance with table 10 . vsov ? overvoltage flag bi t, vsuv / batfail ? under- voltage flag bit, vddt ? vdd voltage regulator status flag bit, and hsst ? high-side status flag bit table 11 indicates the register contents of the following flags: ? vsov flag is set on an overvoltage condition. ? vsuv/batfail flag is set on an undervoltage condition. ? vddt flag is set as pre-warning in case of an overtemperature condition on the voltage regulator. ? hsst flag is set on overtemperature conditions on one of the high-side outputs. l2 and l1 ? wake-up inputs l2 and l1 status flag bit the l2 and l1 flags, as shown in table 12 , reflect the status of the l2 and l1 input pins and indicate the wake-up source. table 9. interrupt status (d7) intscr description 0 spi word read reflects the flag state 1 spi word read reflects the interrupt or wake-up source table 10. lin bus status (d6) linwu/ linfail description 0 no lin bus wake-up or failure 1 lin bus wake-up occurred or lin overcurrent / overtemperature table 11. over- and undervoltage, vdd voltage regulator, and high-side status flag bits (d5, d4, d3, and d2) vsov description vsuv/ batfail description vddt description hsst description 0 v sup below 19 v 0 v sup above 6.0 v 0 no overtemperature 0 hs no overtemperature 1 v sup above 18 v 1 v sup below 6.0 v 1 vdd overtemperature pre-warning 1 hs1, hs2, or hs3 off (overtemperature) table 12. switch input wake-up and real time status (d1 and d0) l2 description l1 description 0 l2 input low 0 l1 input low 1 l2 input high or wake-up by l2 (first register read after wake-up) 1 l1 input high or wake-up by l1 (first register read after wake-up)
analog integrated circuit device data freescale semiconductor 27 33689 typical applications typical applications the 33689 can be configured in several applications. figure 3 shows the 33689 in the typica l master node application. figure 3. 33689 in typical master node application voltage miso rst 5.0 v/50 ma vdd vs1 l1 rxd txd lin physical interface lin gnd hs1 sclk cs l2 e - e+ out window mosi wdc pre-driver hs2 hs3 vs2 watchdog regulator reset control int sense spi and control mode agnd in vcc vs1 op amp tgnd current v dd1 lin bus mcu v bat c3 c4 v dd1 c1 c2 33689 r1 d1 c5 r6 r7 r4 c7 r3 r2 d2 r5 c6 component values c1=47 f c2=c4=c5=100 nf c3=10 f c6=220 pf c7=4.7 nf r1=33 k ? r2 and r3 depend on the application r4>5.0 k ? r5=1.0 k ? r6= 10 k ? r7=2.2 k ? l1 (1) l1 = smd ferrite bead-type tdk mmz2012y202b (1) ext input r8 (1) r8=varistor type tdk avr-m1608c270mbaab (1) notes: 1. l1 and r8 are external components to improve emc and esd performances. 2. freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circui t drawings or tables. while freescale offers component recommendations in this configuration, it is the customer?s responsibility to validate their application.
analog integrated circuit device data 28 freescale semiconductor 33689 packaging packaging dimensions packaging packaging dimensions important for the most current revision of the package, visit www.freescale.com and do a keyword search on the 98a drawing number below. dwb suffix 32-pin soic wide body plastic package 98arh99137a issue b ew suffix (pb-free)
analog integrated circuit device data freescale semiconductor 29 33689 packaging packaging dimensions (continued) packaging dimensions (continued) dwb suffix 32-pin soic wide body plastic package 98arh99137a issue b ew suffix (pb-free)
analog integrated circuit device data 30 freescale semiconductor 33689 revision history revision history revision date description of changes 6.0 6/2006 ? implemented revision history page ? updated outline drawing to revision ?b? ? eliminated all pages (pages 30 to 47) referring to the MC33689Dwb/r2 device ? removed MC33689Dwb/r2 from the orderable parts information ? updated to the prevailing form and style 7.0 8/2006 ? removed MC33689Dew/r2 and replaced with mcz33689dew/r2 in the ordering information block
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